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My talk aims to introduce you our simulation environment called SEP (Simulation and Performance Evaluation). SEP is an incremental component-oriented method to evaluate performances of digital hardware architectures. Structural models are constructed using basic components, connectors and compositional rules. A discrete-event simulation environment allows the performance evaluation of the models relatively to some critical applications. The resulting model may be used as a reference to build VHDL or Verilog code. Firstly, we have defined a generic model using UML (Unified Modelling Language). This model allows an unified modelling of heterogeneous architectures and the definition of a computer-aided graphical environment independent of an architecture type. The behaviour of basic components is actively specified from Java methods. The component-oriented approach allows enhancement of readability and reusability, instruction-set modelling and integration of Esterel modules. Secondly, we advocate the easiness to integrate some validation techniques into our simulation environment thanks to our model properties. In particular, a tool checks composition of components and high-level services. Moreover a dynamic binding mechanism replacing the Java one, efficiently takes care of specified types to perform functional validations. Finally, I planned to make a demonstration of the tool built to validate our method.
