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3:30pm - 4:30pm, Thursday 19th October 2000
Room 2511, James Clerk Maxwell Building
King's Buildings, Mayfield Road
Edinburgh EH9 3JZ.
By 2002, the inexorable advance of Moore's Law will result in capacity for the regular implementation of the 100 million transistor IC. Though only an intellectual milestone, it will enable the integration of system complexity which is currently the domain of hundreds of engineers, multiple companies and years of elapsed time. With more than hundred-times the functional density of devices of only 5 years ago, these devices will be alloys of logic, software and architecture; they will be the true Systems-in-Silicon (True-SoC).
Is it reasonable to expect that the design methods to implement them will be simple evolution of today's logic-centric approaches? Can the re-use model provide the productivity we need, or do we really need a new paradigm?
This seminar will take a closer look at the scope of System-Level Design and the consequence of it on componentisation at a System-Level. The seminar is intended to expose the extent of the problem, and will ask more questions than it answers. But, it will also propose a generic, scaleable, hierarchical, model for System-Level Design and illustrate how even this simple model can be used to provide the answers needed, and to guide the requirements and methods for the Component Industry, System-Integrators, EDA Industry and Academia.
Ian Phillips is Principal Staff Engineer at ARM Ltd. UK. His primary responsibility is to assure an optimal match of ARM's future IP-Product to the evolving market needs. Previously he had worked as designer and manager of systems and components for the MOD, Philips, GEC-Plessey Semiconductors and Mitel Semiconductor. He is a Fellow of the IEE and an active participant in the VSIA.
