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Institute for Computing Systems Architecture

The VAULT/JAMAICA project

Ian Watson
Dept. Computer Science
University of Manchester

VLSI technology is continuing to improve and the billion transistor chip is on the horizon. However, it is not clear that this will support a continuing growth in processor speed. The complexity of super-scalar processor design coupled with clock distribution and power dissipation problems may prevent proper exploitation of the technology potential using current apporaches.

An obvious way to use large numbers of transistors is to build an 'on-chip' multiprocessor, but the history of conventional multi-processors for general applications is discouraging. Either programming is too complex or performance is poor or both.

It is clear that communication is one of the major enemies of good performance in multi-processor systems but maybe the integration of processors 'on-chip' provides an opportunity to address this. Fast communication should ease the problems of extracting implicit parallelism from programs while the emergence of user-level multi-threading in languages such as Java should also help.

The VAULT/JAMAICA project is investigating these issues and has developed a processor architecture which uses fast communication for thread spawning and multi-threading for latency hiding. The seminar will present this architecture and outline the simulator and software systems that have been put in place to evaluate the approach. The sytems are at an early stage of development and the evaluation is preliminary. Nevertheless, we are able to present results from significant applications such as MPEG encode written in Java.


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