Advanced embedded devices such as multi-standard mobile terminals demand for ever-increasing performance and energy efficiency. Simultaneously, a high degree of flexibility and programmability is required due to increasing software complexity and fast changing protocol and codec standards. Hence, application specific instruction set processors (ASIPs) that offer a compromise between these contrary design goals are receiving significant interest as implementation platforms. ASIPs show specialized instruction set architectures, optimized for a particular range of applications. In this presentation, we first present an efficient ASIP design flow that is based on architecture exploration methodology and various synthesis tools. In particular, we highlight automatic generation of C compilers and ISA extensions. Next, we focus on forthcoming multi-processor system-on-chip (MPSoC) platforms. By nature of the application domain and due to the need for energy efficiency, these are highly complex heterogeneous architectures, comprising processors, memories, peripherals, as well as dedicated on-chip communication networks. We describe a methodology and tooling for MPSoC design at high abstraction levels. This methodology supports HW/SW architecture optimization and performance estimation based on virtual system prototypes. Finally, we give an outlook on important future MPSoC research challenges, e.g. programming support, and (re)configurability.