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Massively parallel multi-core systems, particularly SIMD arrays, are no longer the province of the large super computer, but instead they are making their way into a single PC and even embedded processors with applications ranging from video encode/decode to physical modeling.
The CSX architecture provides a novel approach to a new generation of low power/high performance SIMD array processors. Used as either a co-processor to existing systems or integrated as part of a system-on-chip for embedded applications the CSX allows critical sections of an application to be off loaded and computed in parallel.
In the first part of the talk we outline the current and future CSX architectures focusing on the instruction set and system architecture. Moving on to describe an alternative approach to programming these machines with a simple extension to C we are able to model naturally the programming of arbitrary sized multi-core arrays while retaining the semantic completeness of the parent language.
