Home News People Research Study Search

Institute for Computing Systems Architecture

Computer Systems Colloquium

"An execution model for a Chip-multiprocessor using dynamic register allocation and micro-threaded execution"

Chris Jesshope, Massey University, New Zealand

3.30 pm, Thursday 8 June

Room 2511, James Clerk Maxwell Building

Abstract

This talk will briefly introduce the concepts of micro-threaded, pipelined execution in microprocessors and illustrate how this can be used to exploit ILP in sequential code, even in the presence of dependencies. Unlike conventional pipelined and superscaler architectures, this approach requires no speculation to achieve increased ILP or latency tolerance, just explicit compiler generated concurrency. The principles introduced will then be used to explore the design space for a chip-multiprocessor using many simple shared cache/register processors on a single chip.

One of the major problems encountered in this design work was in the resource allocation to threads, which, as in loop unrolling, requires multiple instances of loop bodies as they are unrolled. This is clearly not a scalable solution and requires code to be recompiled for different configurations of processors. The solution that will be presented uses a three-state micro-thread model, where a thread is either unallocated, running, or suspended and in which all local register resources within a thread are allocated dynamically on the transition from unallocated to running. The result is a scheme in which an n-way loop can be unrolled into a n instances of a single body of code which is the thread descriptor. The overhead of generating these n instances will be just one machine cycle and the thread body will contain no conditional branch. In effect a loop is unrolled into one thread from each iteration, with synchronisation and communication being via the shared registers. The handling of dependencies between threads is a major issue in this design and solutions are given in principle, although exact details must be determined by simulation on the number of dependencies allowed per thread.


Home : Colloquium 

Last modified: Mon Dec 6 09:12:44 GMT 1999

Please contact our webadmin with any comments or changes.
Unless explicitly stated otherwise, all material is copyright © The University of Edinburgh.