|
      
|
|
|
|
The system has two phases: first we transform SAFL programs using meaning-preserving transformations to choose the area-time position (e.g. by resource duplication/sharing, specialisation, pipelining) while remaining a high-level specification. After this the FLaSH compiler maps the resultant SAFL program into hardware in a resource-aware manner, that is we map separate functions into separate functional units; functions which are called twice now become shared functional units - accessed by multiplexers and possibly arbiters. The current compiler outputs hierarchical RTL Verilog. We have used the FLaSH system to implement a small commercial processor; we achieve similar gatecounts to two previous RTL and netlist specifications but with around one tenth of the source code.
In this talk, we will address both the SAFL language and resource-aware silicon compilation of SAFL to hardware.
