Schedule Independent Register Allocation for Software Pipelining
Christine Eisenbeis and Sid Ahmed Ali Touati, INRIA, Rocquencourt
- Full Paper(.ps version)
Register allocation in loops is generally carried out after or during the
software pipelining process. This is because doing
the register allocation at first step without assuming a schedule lacks the
information of interferences between values live ranges. The register
allocator introduces extra false dependencies which reduces dramatically the
original ILP. In this paper, we
give a new formulation to carry out the register allocation before the
scheduling process, directly on the data dependence
graph by adding "reuse" edges and analyzing resulting register pressure with respect to the critical cycle. We describe this model in detail and
give an exact formulation for the problem of minimizing register pressure under fixed execution rate constraint, with linear integer programming.
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