Title/Author/Abstract
- Title:
Address Register-Oriented Optimizations for Embedded Processors
- Author:
J. Ramanujam, J. Hong, M. Kandemir and S. Atri
Louisiana State University and The Pennsylvania State University
- Full Paper(.ps version)
- Abstract:
Embedded systems consisting of the application program ROM, RAM, the
embedded processor core, and any custom hardware on a single wafer are
becoming increasingly common in areas such as signal processing.
Given the rapid deployment of these systems, programming on such
systems has shifted from assembly language to high-level languages
such as C, C++, and Java. The processors used in such systems are
usually targeted toward specific application domains, e.g., digital
signal processing (DSP). As a result, these embedded processors
include application-specific instruction sets, complex and irregular
data paths, etc., thereby rendering code generation for these
processors difficult. In this paper, we present new code optimization
techniques for embedded fixed point DSP processors which have limited
on-chip program ROM and include indirect addressing modes using post
increment and decrement operations. Code size can be reduced by taking
advantage of these addressing modes. We first present a size reduction
algorithm. Our solution finds a layout of variables in RAM, so that it
is possible to subsume explicit address register manipulation
instructions into other instructions as a post-increment or
post-decrement operation. Next, we propose an algorithm that uses
commutative transformations to change the access sequence and thereby
reducing the code size. Some DSP cores allow for the post-increment or
decrement value to be larger than one. For such processors, we also
present an approach that is incremental and has some advantages over
another proposed solution that requires the expensive generation of
cliques. Finally, we discuss the use of combined offset assignment
and statement re-ordering to improve code density.
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