Compiler Support for Automatic Performance Modelling
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This talk illustrates how parellelizing compiler technology can be used to greatly simplify and, in many cases, to fully automate the process of applying diverse modeling techniques to model a parallel application. First, we will present the key features of a program workload representation that has been designed to support both compiler synthesis as well as detailed performance prediction. Then, we will present compiler techniques that we used to derive a concise form of this workload description automatically for a given program. The focus of these techniques is HPF programs compiled to MPI using the Rice dHPF compiler - issued related to explicit message-passing codes will also be discussed.
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