Title/Author/Abstract
- Title:
Minimizing Strides in Loops with Affine Array References
- Author:
Ph. Clauss, V. Loechner, B. Meister
ICPS/LSIIT, Universite Louis Pasteur, Strasbourg, France
- Full Paper(.ps version)
- Abstract:
A significant source of enhancing application performance and of reducing
power consumption in embedded processor applications is to improve the usage
of the memory hierarchy. In this work, a temporal and spatial locality
optimization framework of nested loops is proposed, driven by parameterized
cost functions. The considered loops can be imperfectly nested. New data
layouts are propagated through the connected references and through the loop
nests as constraints for optimizing the next connected reference in the same
nest or in the other ones. Unlike many existing methods, special attention is
paid to TLB (Translation Lookaside Buffer) effectiveness since TLB misses can
take up to three times more cycles than a cache miss. Our approach only
considers active data, i.e. array elements that are actually accessed by a
loop, in order to prevent unuseful memory loads and take advantage of storage
compression and temporal locality. Moreover, the same data transformation is
not necessarily applied to a whole array. Depending on the referenced data
subsets, the transformation can result in different data layouts for a same
array. This can significantly improve the performance since a priori
incompatible references can be simultaneously optimized. Finally, the process
does not only consider the innermost loop level but all levels. Hence, large
strides when control returns to the enclosing loop are avoided in several
cases, and better optimization is provided in the case of a small index range
of the innermost loop.
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