Computer Architecture Simulation Models

Simulation models of a variety of computer architectures and architectural components have been created using HASE, a Hierarchical Computer Architecture design and Simulation Environment. These models are intended for use as teaching and learning resources: in lectures, for student self-learning or for virtual laboratory experiments (†).

Using the models requires use of HASE itself. The latest (Java) version of HASE is available for Linux, MAC OS X and Windows and can be downloaded from the Downloading, Installing and Using HASE web page.

Each model has its own supporting website describing the system being modelled as well as the model itself. The source files for each model can be downloaded from the relevant website as a model_name.tar.gz file. These files provide the input to HASE which has options to load a project, to compile a simulation executable and to run the simulation. Running a simulation produces a trace file which can be used to animate the on-screen display of the model so as to show data movements, parameter value updates, state changes, etc.

The following computer architecture models are currently available.

• Microcodable Processor   (EMMA - Edinburgh Microcoded Microprocessor Architecture)
• Simple Pipelined Processor   (based on MIPS)
• Processors with Scoreboards   (based on DLX and MIPS)
• Processor with Predication   (based on DLX)
• SIMD Array Processors
• Tomasulo's Algorithm
• Two-level Cache Model   (based on Stanford DASH Node)
• Snoopy Cache Coherence   (Write Invalidate)
• Directory-based Cache Coherence   (CD/SDD/SCI)
• Cache Coherence   (based on Stanford DASH Cluster)

† Some of these models were previously available as applets but using the models directly in the downloadable version of HASE has proved more satisfactory.

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